This invention relates generally to delay-locked-loops.
As is known in the art, delay-locked-loops are used in a wide variety of applications in order to produce an output signal in-phase with a received signal, such as a train of input pulses. One such application is shown in FIG. 1 where an input train of pulses, such as system clock pulses, SYS.sub.-- CLK, are received by a receiver 12 (i.e., buffer) of an integrated circuit chip. The receiver 12 imparts a finite time delay, .DELTA., to the received pulses. In order to produce an output train of pulses in phase alignment with the input clock pulses (i.e., in order to maintain a predetermined phase relationship between the output train of pulses and the input clock pulses), a delay-locked-loop (DLL) 14 is sometimes provided. The delay-locked-loop 14 includes a phase comparator 16, a variable, typically digitally controlled, delay line 18, and a fixed delay 20. The fixed delay 20 has the same delay, .DELTA., as the receiver 12. The output of the receiver 12 (i.e., input to the DLL 14) is fed to one input 22 of the phase comparator 16 and the output of the DLL 14 is fed to another input 24 of the phase comparator 16. In the steady-state, the output of the phase comparator 16 will force the time delay of the digitally controlled delay line 18 to a time delay nT-.DELTA., where T is the period of the clock pulses fed to the receiver 12 and n is an integer. That is, the output of the variable delay line 18 is feedback to input 24 of the phase comparator 16. The output of the phase comparator is a phase error signal. The phase error signal drives the delay of the delay line 18 such that the error is driven to zero. Thus, in the steady-state, (i.e, when the phase error is driven to zero) the total time delay through the receiver 12 and the delay line 18 is .DELTA.+(nT-.DELTA.)=nT. That is, the train of pulses produced at the output of the digitally controlled delay line 18 (i.e., the output of the DLL) will, in the steady-state, be in-phase, or time-aligned (i.e., timed coincident) with the train of SYS.sub.-- CLK clock pulses received by the receiver 12. As is known each pulse has a leading edge followed by a trailing edge. These edges are of different edge types, i.e., the leading edge may be a rising edge type in which case the trailing edge will be a falling edge type; or, on the other hand, the leading edge may be a falling edge type in which case the trailing edge will be a rising edge type.
As is also known in the art, some digital devices operate in response to both leading and trailing edges of the clock pulses. For example, Double-Data-Rate Synchronous Dynamic Random Access Memories (DDR-SDRAMs), require timing specifications to both the leading and trailing edges of clock pulses fed to such DDR-SDRAMs. More particularly, when system clock pulses are fed to the DDR-SDRAM chip, the pulses are received by a receiver on the chip. The receiver provides a time delay to the clock pulses. To compensate for this time delay, a DLL is sometimes used. As noted above, the DLL may include a digitally controlled delay line. One such delay line includes both n-channel field effect transistors (NFETs) and p-channel field effect transistors (PFETs). Due to processing variations, the amount of current the PFET can source relative to the NFET varies thereby causing skew between propagation of rising and falling edge types in a PFET/NFET delay line (i.e., the rise delay of a clock pulse is different from the fall delay of the clock pulse). This introduces "jitter" in a DLL system and detracts from maximum operating objective data rate, for example, a data rate of 200 MHz. For a typical delay line length of 5 nanoseconds (ns) for a 100 MHz clock, such processing variation effects can modulate rising and falling delays by approximately 0.5 ns.